a ad7861 functional block diagram ref in busy ref out vin1 vin2 vin3 a0 a1 d0 d11 rd cs clkin sha 2.5v reference aux0 aux1 aux2 aux3 s0 s1 convst reset m0 m1 12 11-bit adc 4-1 mux output registers sgnd agnd dgnd v dd ad7861 11-bit resolution simultaneous sampling a/d converter information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. features 11-bit resolution analog-to-digital converter seven single-ended analog inputs four input channels simultaneously sampled expansion with 4 multiplexed inputs internal 2.5 v reference 3.2 s conversion time per channel user definable channel sequencing single supply +5 v operation double buffered register outputs 6.25 mhz to 12.5 mhz operating clock range applications motor control 3-phase power measurement cellular phones data acquisition general description the ad7861 is a multichannel simultaneous sampling a/d converter (adc) configured for the acquisition of voltage inputs in a motor control solution or three-phase power system. the ad7861 combined with analog devices?16-bit fixed- point digital signal processor (dsp) provides a low cost 16-bit fixed-point microcontroller solution. the input stage has been designed to accommodate the types of signals frequently found in motor drives. the vin1, vin2, and vin3 channels are simultaneously sampled inputs suitable for stator current acquisition. the aux0?ux3 channels are multiplexed and are suitable for slower moving inputs such as temperature and bus voltage of the diode rectifier output in a motor control application. product highlights simultaneous sampling of four inputs four channel sample and hold amplifier (sha) allows out of phase input signals to be sampled simultaneously, preserving the relative phase information. sample-and-hold acquisition time is 1.6 s and conversion time per channel is 3.2 s (using a 12.5 mhz system clock). flexible analog channel sequencing ad7861 supports acquisition of 2, 3 or 4 channels per group. converted channel results are stored in registers and the data can be read in any order. the sampling and conversion time for two channels is 8 s, three channels is 11.2 s, and four channels is 14.4 s (using a 12.5 mhz system clock). single 5 v dc operation low power, digital process. rev. b one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000
ad7861* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. documentation data sheet ? ad7861: 11-bit resolution simultaneous sampling a/d converter data sheet reference materials technical articles ? ms-2210: designing power supplies for high speed adc design resources ? ad7861 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad7861 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad7861?pecifications parameter ad7861ap units conditions/comments dc accuracy resolution 11 bits twos complement data format relative accuracy 2 lsb max integral nonlinearity differential nonlinearity 2.5 lsb max bias offset error 9 lsb max any channel bias offset error match 4 lsb max between channels full-scale error 13 lsb max any channel full-scale error match 4 lsb max between channels dynamic performance signal-to-noise ratio (snr) 60 db min f in = 1 khz sine wave, f sample = 75 khz total harmonic distortion (thd) ?0 db max f in = 1 khz sine wave, f sample = 75 khz peak harmonic or spurious noise ?0 db max f in = 1 khz sine wave, f sample = 75 khz channel-to-channel isolation m1 = 0 ?8 db max 1 khz sine wave applied to unselected channels m1 = 1 ?3 db max 1 khz sine wave applied to unselected channels reference input voltage range (ref in) 2.5 v input current 50 a max onboard reference output (ref out) 2.5 v reference tolerance 5% reference drive capability 100 a max sample-and-hold acquisition time 1.6 s 20 clk cycles @ 12.5 mhz aperture delay time 200 ns max aperture delay time match 20 ns max droop rate 5 mv/ms max logic input high voltage (v ih ) 2 v min input low voltage (v il ) 0.8 v max input leakage current 1 a max input capacitance 20 pf typ (v oh ) 4.5 v min i source current = 20 a, v dd = 5 v (v ol ) 0.4 v max i sink current = 400 a, v dd = 5 v three-state leakage current 1 a max conversion rate conversion time/channel 40 clk cycles convst pulsewidth 2 clk cycles min analog inputs nominal input level 0? v vin1, vin2, vin3, aux0?ux3 input current 100 a input capacitance 10 pf system clock 6.25?2.5 mhz power requirements v dd 5v dc i dd 10 ma max rev. b ?2 (v dd = 5 v 5%; t a = ?0 c to +85 c; refin = 2.5 v; ext clk @ 12.5 mhz, unless otherwise noted)
ad7861 rev. b ? table i. ad7861 timing parameters (t a = ? 0 c to +85 c and v dd = +5 v unless otherwise noted) number symbol ad7861 timing requirements min max units 1t su csb_rdb cs low before falling edge of rd 0 ns 2t su addr_rdb addr valid before falling edge of rd 0 ns 3t dly rdb_data data valid after falling edge of rd ?5ns 4t pwl rdb rd pulsewidth, low 25 ns 5t pwh rdb rd pulsewidth, high 25 ns 6t hd rdb_data data hold after rising edge of rd 10 ns 7t hd rdb_addr addr hold after rising edge of rd 0 ns 8t hd rdb_csb cs hold after rising edge of rd 0 ns 9t per clk clk period 80 160 ns 10 t pwh clk clk pulsewidth, high 20 ns 11 t pwl clk clk pulsewidth, low 20 ns 12 t pwl resetb reset pulsewidth, low 2 tperclk ns 7, 8 3 1, 2 clk cs a0?1 rd data bus 6 4 5 figure 1. clock and reset timing 9 10 11 clk 12 clk reset figure 2. write cycle timing diagram caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7861 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide model temperature range package option ad7861ap ?0 c to +85 c p-44a absolute maximum ratings* supply voltage (v dd ) . . . . . . . . . . . . . . . . . . ?.3 v to +7.0 v digital input voltage . . . . . . . . . . . . . . . . . . . . . ?.3 v to v dd analog input voltage . . . . . . . . . . . . . . . . . . . . . ?.3 v to v dd analog reference input voltage . . . . . . . . . . . ?.3 v to v dd digital output voltage swing . . . . . . . . . . . . . . ?.3 v to v dd analog reference output swing . . . . . . . . . . . ?.3 v to v dd operating temperature . . . . . . . . . . . . . . . . . ?0 c to +85 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +280 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device
ad7861 rev. b 4 pin description pin mnemonic type description 1 aux0 i/p auxiliary input 0 2 refin i/p analog reference input 3 agnd gnd analog ground 4 refout o/p internal 2.5 analog reference 5 s0 i/p aux channel select 0 6 s1 i/p aux channel select 1 7 d0 o/p data bit 0 lsb (tied low) 8 d1 o/p data bit 1 9 d2 o/p data bit 2 10 d3 o/p data bit 3 11 d4 o/p data bit 4 12 d5 o/p data bit 5 13 d6 o/p data bit 6 14 d7 o/p data bit 7 15 d8 o/p data bit 8 16 d9 o/p data bit 9 17 d10 o/p data bit 10 18 d11 o/p data bit 11, msb 19 dgnd gnd logic ground 20 dgnd gnd logic ground 21 v dd sup +5 v digital supply 22 m0 i/p conversion mode select 0 23 m1 i/p conversion mode select 1 24 convst i/p a/d conversion start 25 cs i/p chip select 26 rd i/p read input 27 reset i/p chip reset 28 a1 i/p register address select 1 29 a0 i/p register address select 0 30 nc nc no connect 31 busy o/p busy, conversion in process 32 clk i/p external clock input 6.25 mhz-12.5 mhz 33?4 dgnd gnd logic ground 35 sgnd gnd signal ground 36 v dd sup +5 v analog supply 37 vin1 i/p analog input 1 38?9 nc nc no connect 40 vin2 i/p analog input 2 41 vin3 i/p analog input 3 42 aux3 i/p auxiliary input 3 43 aux2 i/p auxiliary input 2 44 aux1 i/p auxiliary input 1 pin configuration 18 19 20 21 22 23 24 25 26 27 2 8 35 36 37 38 39 33 34 31 32 29 30 2144 3 4 5 6424140 43 9 10 11 12 13 7 8 16 17 14 15 pin 1 identifier top view (not to scale) ad7861 rd reset a1 nc nc vin1 v dd sgnd dgnd dgnd m1 d11 dgnd dgnd v dd m0 convst d0 d1 d2 d3 d4 d5 d6 nc = no connect d7 d8 d9 d10 clk busy nc a0 cs s1 s0 refout agnd refin aux0 aux1 aux2 aux3 vin3 vin2 pin types pin types i/p = input pin gnd = ground pin o/p = output pin sup = supply pin
ad7861 rev. b 5 analog input block the ad7861 is an 11-bit resolution, successive approximation analog-to-digital (a/d) converter with twos complement output data format. the analog input range is 0 v? v with a 2.5 v reference as defined by the reference input pin (refin). the ad7861 has an internal 2.5 v 5% reference, which is utilized by connecting the reference output pin (refout) to the refin pin. the a/d conversion time is determined by the system clock frequency, which can range from 6.25 mhz to 12.5 mhz. forty clock cycles are required to complete each conversion. there is a 4-channel simultaneous sample and hold amplifier (sha) at the ad7861 input stage. this allows up to 4 channels to be simultaneously held and sequentially digitized. the sha acquisition time is 20 clock cycles and is independent of the number of channels sampled. the minimum throughput time can be calculated as follows: t aa = t sha + ( n t conv ) where t aa = analog acquisition time, t sha = sha acquisition time, n = # channels, t conv = conversion time per channel (40 clock cycles). a/d conversions are initiated by an external analog sample clock pin (convst). the convst input can be run asynchronous to the ad7861 system clock. when convst is run asynchronous from clk, the falling edge of clk subsequent to convst high initiates the conversion. busy the ad7861 busy pin goes low at the start of conversion, and remains low for 40 clock cycles per channel. when busy goes high, this indicates that the output data buffers have been updated. data from the previous conversion can be read up to (n 40 1) clock cycles after the start of conversion (n = number of channels converted). refer to figure 3. t = 1 clock cycle t = (n x 40 1) clock cycles t = n x 40 clock cycles (n x 40 1) clock cycles old data valid new data valid clk busy convst data figure 3. busy pulse timing channel selection determining which channels are converted is dependent on the settings of m0 and m1. the available channel combinations are: m1 m0 channels converted 0 0 vin2, vin3 0 1 vin2, vin3, aux 1 0 vin1, vin2, vin3 1 1 vin1, vin2, vin3, aux the user must select which channels to convert using m0/m1, a minimum of two clock cycles before the start of conversion. the ad7861 provides 4 auxiliary input channels which can be individually multiplexed into the auxiliary adc channel. pins s0/ s1 are used to multiplex these auxiliary channels according to the following table. it is important to note that the adc performs a series of conversions based on the input voltage on each pin (including the aux pin) at the start of the convst conversion pulse. the user must select the auxiliary chan nel using s0/s1 a minimum of two clock cycles before the start of the conversion sequence. s1 s0 channel selected 0 0 aux0 0 1 aux1 1 0 aux2 1 1 aux3 digital interface the ad7861 is designed to interface with the adsp-21xx family of dsps. the 12-bit parallel interface can also be used with other dsps and microcontrollers. the 11-bit a/d conversion output occupies the 11 most significant bits of the 12-bit interface. the lsb (data bit 0) is tied low. register based input/output to facilitate integration into most designs, a register based input/output structure is provided. these registers can be memory mapped into the user s system along with other memory mapped peripherals. register addressing two address lines (a0 through a1) are used in conjunction with control lines ( cs , rd ) to select registers vin1, vin2, vin3, or aux. these control lines are active low. timing and logical sense is as for the adsp-2100 family. pin function cs enables the ad7861 register interface rd places the internal register on the data bus register listing the output of each channel is stored in its respective register. the symbolic names and address locations are listed in the following table. name a1 a0 register function vin1 0 0 a/d conversion result channel vin1 vin2 0 1 a/d conversion result channel vin2 vin3 1 0 a/d conversion result channel vin3 aux 1 1 a/d conversion result channel aux
ad7861 rev. b 6 description of the registers vin1, vin2, vin3 t hese registers contain the results from the conversion of the analog input voltages. aux in the ad7861, this register contains the conversion result of the auxiliary channel which had been selected by s0, s1. reading results the a/d conversion results for channels vin1, vin2, vin3 and aux are stored in the vin1, vin2, vin3 and aux registers respectively. the twos complement data is left justified and the lsb (data bit 0) is set to zero. the relationship between input voltage and output coding is shown in figure 4. 011111111110 000000000000 100000000000 output code full-scale transition 0v 2.5 5v-1lsb input voltage fs = 5v lsb = 5v 2048 figure 4. ad7861 transfer function power supply connections and setup the nominal power supply level (v dd ) is +5 v 5%. the positive power supply (v dd ) should be connected to pins 21 and 36. the sgnd and dgnd pins should be star point connected to agnd at a point close to the ad7861. power supplies should be bypassed at the power pins using a 0.1 f capacitor. a 200 nf capacitor should also be connected between refin and sgnd. c2073a 1.5 3/00 (rev. b) printed in u.s.a. digital signal processor interfacing the ad7861 a/d converter is designed to be easily interfaced to analog devices family of digital signal processors (dsps). figure 5 shows the interface between the ad7861 and the adsp-2101/2105/2115 16-bit fixed point dsp, and the adsp- 2171 and adsp-2181 dsp microcomputers. flagout from the dsp is used to initiate the ad7861 conversion and is also used in conjunction with the busy signal to provide an end of conversion interrupt for the dsp. with m0 and m1 tied low, the ad7861 is set up in the vin2, vin3 channel conversion mode. by mapping the 12-bit ad7861 data bus into the top 12 bits of the dsp data bus (d12 d23), full-scale outputs from the ad7861 can be represented as 1.0 in fixed point arithmetic. the ad7861 can operate with a clock frequency in the range of 6.25 mhz to 12.5 mhz. for the adsp-2101/2105/2115 the clkout frequency is the system clock frequency. in the case of the adsp-2171/2181, the system clock is internally scaled, a 10 mhz system clock will result in a 20 mhz clkout frequency. if clkout from the adsp-2171/2181 is above 12.5 mhz, then an external clock divide down circuit will be necessary. dms irq2 rd clkout d0 d23 a0 a13 adsp-2101/ adsp-2105/ adsp-2115 12mhz adsp-2181 10mhz adsp-2171 10mhz cs busy rd clk d0 d11* a0 a1 ad7861 address bus data bus m0 flagout en address decode convst m1 figure 5. adi digital signal processor/microcomputer interface outline dimensions dimensions shown in inches and (mm). 44-lead plastic leadless chip carrier (p-44a) 6 pin 1 identifier 7 40 39 17 18 29 28 top view (pins down) 0.695 (17.65) 0.685 (17.40) sq 0.656 (16.66) 0.650 (16.51) sq 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.020 (0.50) r 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) bsc 0.63 (16.00) 0.59 (14.99) 0.032 (0.81) 0.026 (0.66) 0.180 (4.57) 0.165 (4.19) 0.040 (1.01) 0.025 (0.64) 0.025 (0.63) 0.015 (0.38) 0.110 (2.79) 0.085 (2.16) 0.056 (1.42) 0.042 (1.07)
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